1. Field of the Invention
The present invention relates to a semiconductor device having an impurity diffusion layer of a second conductivity type formed in a shallow region within a semiconductor layer of a first conductivity type.
2. Description of the Related Art
In recent times, electronic devices such as computers and communication equipment have been employing as their key circuit components large scale integrated circuits (LSI) in which a number of circuit elements, such as transistors and resistors, are integrated into a semiconductor substrate. In this technical field, the problem of how to increase the integration density of an LSI is one of the most important currently being faced. To increase the integration density, it is necessary to further reduce the size of each circuit element, such as a MOS type field effect transistor (FET). One approach to realizing this has been to reduce the FET gate length, since a reduced gate length leads to a reduction in the total chip area occupied by FETs. However, the threshold voltage of the FET must be kept unchanged even if the gate length is reduced. To this end, a shallow source/ drain region must be formed in the semiconductor substrate.
Low acceleration ion implantation has hitherto been the dominant method employed for forming the diffusion layer of a MOS FET. Recently, however, a diffusion process using an impurity--for example, As (arsenic)--has also been used for this purpose. This process succeeds in realizing a shallow source/drain region of about 0.1 .mu.m in depth for the n.sup.+ /p junction. The resultant MOS FET is reduced in size and high in performance. As for the p.sup.+ /n junction, after the surface layer of the single-crystal silicon has been made amorphous by Si.sup.+, Ge.sup.+, Sn.sup.+ ion implantation, it is subjected to a low acceleration BF.sub.2 implantation. This process realizes a shallow source/drain region of approximately 0.1 .mu.m in depth even after annealing for activation has been carried out.
A diffusion layer about 0.1 .mu.m deep has a high resistance and its sheet resistance is 100 ohms/.quadrature. or more. However, to increase the operation speed of the semiconductor element, the diffusion layer surface must be metallized to reduce its resistance.
Recently, an attempt has been made to form a metal silicide on a diffusion layer. In the process, an impurity diffusion layer is formed in an silicon exposed region, Ti (titanium) or Co (cobalt) is deposited over the entire surface of the substrate, titanium silicide or cobalt silicide is formed only on the silicon layer into which an impurity has been diffused by ramp annealing, and an unreactive Ti or Co film is etched away. When a silicide of 50 nm in depth, for example, is formed by this process, the sheet resistance is reduced to 3 to 5 ohms/.quadrature..
A conventional method of manufacturing MOS FETs by using a metal silicide will be described below, with reference to FIGS. 1A to 1D.
To start with, a field oxide film 12 is formed in an n-type Si substrate 11. A multilayer consisting of a gate oxide film 13 of 100 .ANG., a polysilicon layer 14a of 1000 .ANG. doped with As, a tungsten silicide layer 14b of 3000 .ANG., and an SiO.sub.2 film 15 of 1500 .ANG. is shaped like a gate-electrode, by use of an etching process, within a region of the substrate enclosed by the oxide film 12. Thereafter, the side wall of the gate electrode portion is covered with an SiO.sub.2 film 17. Cobalt is deposited over the entire surface of the structure, to form a Co film 19 of 300 .ANG. thickness. The resultant structure is annealed in argon gas to form a CoSi layer of 700 .ANG., and is then immersed in a liquid composed of a mixture of hydrogen peroxide and hydrochloric acid, to remove the unreactive Co film 19. Thereafter, the structure is annealed in Ar gas, to form a CoSi.sub.2 layer 20 of 1000 .ANG. thickness, as shown in FIG. 1B.
As shown in FIG. 1C, B.sup.+ ions are implanted into the structure, over its entire surface and under the conditions of 10 KeV of acceleration voltage and 5.times.10.sup.15 cm.sup.-2 of dosage. As a result, the CoSi.sub.2 layer 20 is doped with boron. Then, the structure is annealed at 850.degree. C. and for 30 minutes in Ar gas, so that the boron is thermally diffused under the CoSi.sub.2 layer 20, to form a p.sup.+ layer 16 i.e., a source/drain region, about 0.1 .mu.m thick. Subsequently, interlayer insulation film deposition, contact hole opening, and interconnection wiring are successively performed, to complete the MOS FET. In this way, a p+diffusion layer 0.1 .mu.m thick and covered with a CoSi.sub.2 layer 0.1 .mu.m thick (of 1.5 ohms/.quadrature.) is formed.
However, the process set out above has the following drawbacks.
As described above, after the CoSi.sub.2 layer 20 is formed, boron is thermally diffused into the substrate 11 thereunder, as a diffusion source of the layer 20, thereby to form the p.sup.+ layer 16. Therefore, the layer 16 is necessarily deeper than the CoSi.sub.2 layer 20. Since the depth of the source/drain region is equal to the sum of the thickness of the layer 20 and that of the layer 16, the depth of the source/drain region is therefore substantial.
When a native oxide film of the Si surface and a surface contaminated and damaged layer resulting from the dry etching are both present, it is difficult for the silicide to react uniformly. Therefore, if an impurity is later doped into the structure, the boundary structure will be nonuniform, as shown in FIG. 2. In the nonuniform boundary structure, local concentrations of electric fields tend to occur. At the locations or the pn junctions where the electric field is concentrated, the leakage current increases, and in an extreme case, the pn junction is destroyed. For this reason, when the above-described process is used, it is very difficult to form the pn junction of 0.1 .mu.m or less deep.
In the case of the micro-transistors under the design rule of 0.3 .mu.m or less, the total thickness must be 0.1 .mu.m or less. To reduce the total thickness, it is necessary to reduce the thickness of the silicide and further to form a diffusion layer of several hundreds Angstroms under the silicide. However, if the silicide is thinned, resistance of the source/drain region increases. When the thickness of the diffusion layer is 500 .ANG. or less, the pn junction characteristic is deteriorated. The causes for the junction deterioration are: 1) A GR (Generation Recombination) center distribution due to the metal distribution influences the junction characteristic so that the diffusion layer is within the thickness where the junction current leakage is observed; 2) When the diffusion layer is thinned, the configuration of the diffusion layer clearly reflects the irregularity of the silicide/Si interface, and accordingly, the electric field concentration tends to occur; 3) The ballistic conduction tends to occur.